FUNCTIONAL BLOCK DIAGRAM OF NE555

In this we are going to study about functional block diagram of ne555. It is also called 555 timer. This IC used for generating accurate time delay or oscillation. The maximum operating frequency is excess of 500kHz. The 555 timer can be used with supply voltage in the range from +5V to +18V and can drive load up to 200mA.




Functional diagram of 555




The 5K intrenal resistance act as a voltage devider network, providing (2/3) Vcc at inverting terminal of upper comparator (UC) and (1/3)Vcc at the noninverting terminal of lower comparator (LC). In the stable state , the Q*(Q bar) output of the control flip flop is high. This makes the output low because of the buffer which basically is an inverter.


Pin 1 - It is ground

Pin 2 (Trigger) - This pin is used to feed the trigger input when the chip is set up as a monostable multivibrator. When a trigger of amplitude greater than (1/3)Vcc is applied to this terminal , circuit switches to quasi stable state.

Pin 3 - This is output

Pin 4 (Reset) - This terminal is used to reset the output of the circuit irrespective of th input. A logic low input will be reset the output. For normal operation this pin is connected to Vcc.

Pin 5 (Control) - Viltage applied to this terminal will control the instant at which the comparator switches and hence the pulse width of the output. When this pin is not used it is bypassed to ground using a 0.01μF capacitor.

Pin 6 (Threshold) - If the voltage applied to the threshold terminal is greater than (2/3)Vcc, upper comparator switches to +Vsat and flip flop output get reset.